`include "HalfAddr.v"
module HalfAddr_tb;
    reg a, b;
    wire sum, carry;
    HalfAddr halfAddr1(a, b, sum, carry);

    initial begin
        a = 0;
        b = 0;
    end
    initial begin
        $monitor("a = %b, b = %b, sum = %b, carry = %b", a, b, sum, carry);
    end
    initial begin
        #10 a = 1;
        #10 b = 1;
        #10 a = 0;
        #10 b = 1;
        #10 a = 1;
        #10 b = 0;
    end
endmodule       